Electrical and Computer Engineering The University of Texas at Austin .
Cell size accounts for most of array size Reduce cell size at expense of complexity 6T SRAM Cell Used in most commercial chips Data stored in cross. .
Pre-charge & equalize bit-lines from previous cycle Minimum “Design Margin” before next READ begins Delay requirement to allow sufficient bit-line voltage development BL Equalization BL# Degradation Due to & Restore Spec Quiet WL(s) + coupling VDD SA. .
Memory Arrays Random Access Memory Serial Access Memory Content Addressable Memory (CAM) Read/Write Memory (RAM) (Volatile) Static RAM (SRAM) Dynamic RAM. .
Source: Kelin Kuhn, Intel SRAM Memory Cell Improvements
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